RISC vs CISC
Mar 10 '00
There are many arguments concerning the advantages of RISC over CISC or the other way around. Right now the Macintosh line of computers advertises that their G3/G4 Motorola 7400 chips are RISC while Intel and AMD are stuck with the slower CISC variety.
RISC means "reduced instruction set computing" while CISC means "complex instruction set computing." Before we compare, I'd just like to say that RISC does not really mean "reduced instruction set" any more than CISC means that the instructions are more complex.
CISC is a philosophy for designing CPUs that are easy to program. Each variable width instruction might perform a series of operations within the processor. The CISC philosophy might include the use of microcode, as well as rich and high level instruction sets, which might map directly to high level languages. Engineers often added a plethora of obscure instructions to a CISC processor, not knowing what might or might not be of use to the coder. In fact, many of the most used CISC instructions are often shorter and simpler than their RISC counterparts.
In the mid seventies, as memory and processor speed grew, a need was seen for the idea a simpler instructions. The philosophy of RISC came about which uses fixed bandwidth instructions and pipelining, so that an instruction can be fetched in a single operation. RISC processors are very compiler intensive in that the compiler must arrange instructions for the pipeline in the proper order so that the processor does not stall.
Remember, the whole concept of RISC and CISC isn't really a specification, but more of a philosophy of design. Do today's Power PC line of Motorola 7400 chips meet the design philosophy of RISC, and do Intel's and AMD's line of CPUs match the older CISC philosophy? I would say, "No" to both. Today is the era of the post-RISC CPU as defined by Dr. Charles Severance of the University of Michigan Department of Engineering Computer Services College of Engineering. Severance points to the modern trend of CPUs to use techniques not found on traditional RISC processors such as non-compiler intensive speculative execution and register renaming in conjunction with instruction retirement.
The concept of Post-RISC design has little or nothing to do with the Intel/AMD vs. Mac platform war, as one might have it. The whole concept of CISC, RISC and Post-RISC is an academic definition that goes beyond the hype of Intel and Apple advertising or the platform evangelists and advocates on both sides. The Motorola 604e, G3, G4, MIPS as well as the PIII and Athlon could all be classed as Post-RISC technology. In fact, in light of the way processors are designed today with the problems and solutions addressed, both RISC and CISC are both ridiculous terms to use in discussion of the designs of the G3, G4, MIPS, P6, or K7 processors. Whatever argument about the merits of RISC or CISC is long over in this Post-RISC era and each Post-RISC design must be considered for the way it solves the modern problems of today's computing.
Sources:
Charles Severance PhD Standards Column Editor for IEEE Computer
Director of the Division of Engineering Computer Services (DECS) in the MSU College of Engineering
High Performance Computing from O'Reilly and Associates
http://www.egr.msu.edu/~crs/archive.html
Authors: Mark Brehob, Travis Doom, Richard Enbody, William H. Moore, Sherry Q. Moore, Ron Sass, Charles Severance Michigan State
University Department of Computer Science
Submitted to IEEE Micro May 1996 Submitted to IEEE Computer May 1997
http://www.egr.msu.edu/~crs/papers/postrisc2/
Beyond RISC - The Post-RISC CPU Draft
http://www.egr.msu.edu/~crs/papers/cas_920/
The G4 and the K7: an architectural look at two post-RISC processors
Jon "Hannibal" Stokes
http://www.arstechnica.com/cpu/1q00/g4vsk7/g4vsk7-1.html
RISC vs. CISC: the Post-RISC Era
Jon "Hannibal" Stokes jstokes@arstechnica.com
http://arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html
John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Second Edition. Morgan Kaufmann Publishers, Inc. San Francisco, CA. 1996.p9.
http://arstechnica.com/etc/books/comp-arc.html
http://infopad.eecs.berkeley.edu/CIC/summary/local/
x86 Emulation 7th Generation CPU Comparisons by Paul Hsieh
http://www.azillionmonkeys.com/qed/cpujihad.shtml
 |
|
|
|
|
|
|
Epinions.com ID:
GuideNet
|
|
Member: Craig Harding
Location: Orlando, Florida
Reviews written: 2
Trusted by: 0 members
|
|
|
© 1999-2010 Shopping.com, Inc.